The present invention relates to a nonvolatile semiconductor memory device, and more particularly relates to a non-volatile semiconductor memory device including gate electrodes in two layers, i.e., control and floating gates, and functioning as a flash memory.
Memories so constructed as to erase specified data electrically at a time, like a flash memory, have been in higher and higher demand these days.
As is well known in the art, various factors make it difficult for a flash memory to ensure high reliability. A so-called xe2x80x9ccharge buildup damagexe2x80x9d is one of those factors that decrease the reliability of a flash memory. The charge build-up damage is done on the tunnel insulating film of a flash memory during a metallization process to fabricate the memory. More specifically, when metal interconnects are formed by dry etching and patterning processes, positive or negative electric charges are likely accumulated in the interconnects. And if the quantity of those charges accumulated is huge, the control gate of the memory will have a potential with an outstandingly large absolute value, thus placing an excessively intense electric field on the tunnel insulating film. Should damage of that type be done on the tunnel insulating film, the reliability of a memory cell of the flash memory would decrease considerably.
For that reason, methods for reducing the charge buildup damage during a metallization process have been researched and developed vigorously in the pertinent art.
Hereinafter, one such method for reducing the charge buildup damage in a metallization process will be described.
FIG. 13 illustrates a memory cell for a flash memory (which will be herein called a xe2x80x9cflash memory cellxe2x80x9d simply) and a known charge buildup damage reducer. As shown in FIG. 13, a flash memory cell 101 has its control gate connected to a word line decoder 102 and to the cathode of a charge buildup damage reducer 103. The charge buildup damage reducer 103 is implemented as a backward diode with a grounded anode.
FIG. 14 illustrates a cross-sectional structure for the damage reducer 103. As shown in FIG. 14, a p-well 111 is defined in the upper part of a p-type semiconductor substrate 110. Over the p-well 111, n- and p-type doped regions 113 and 114 are defined and electrically isolated from each other by an isolation film 112. The n-type doped region 113 is connected to the control gate of the flash memory cell 101, while the p-well 111 and p-type substrate 110 are grounded by way of the p-type doped region 114.
FIG. 15 illustrates a current-voltage (I-V) characteristic of the damage reducer 103 (i.e., backward diode). In FIG. 15, the abscissa represents the voltage VCG applied to the control gate, while the ordinate represents the current Idiode flowing from the n-type doped region 113 into the p-well 111 in the backward diode 103. As shown in FIG. 15, if the voltage VCG applied to the control gate is V11 (e.g., about xe2x88x920.6 V) or less, a forward bias is applied to the backward diode 103. As a result, a current starts to flow through the backward diode 103. On the other hand, if the voltage VCG applied to the control gate is V12 (e.g., about 15 V) or more, breakdown occurs at the backward diode 103 and a current also starts to flow through the diode 103. That is to say, while the voltage VCG is between V11 (about xe2x88x920.6 V) and V12 (about 15 V), no current flows through the backward diode 103.
Next, it will be described how the known charge buildup damage reducer operates.
In a gate grounded erase method, in which electrons are removed from the floating gate by applying 0 V and 12 V to the control gate and source electrode, respectively, during erasing, the voltage applied to the control gate is always between 0 V and 12 V irrespective of the mode of operation the flash memory cell. No current flows through the backward diode within this voltage range, and the operation of the flash memory cell is not interfered with.
On the other hand, during the metallization process, positive or negative electric charges build up in the control gate of a flash memory cell. However, the known charge build-up damage reducer 103, or the backward diode 103, is connected to the control gate of the flash memory cell 101. Accordingly, if the voltage applied to the control gate is V11 or less or V12 or more, the charges built up flow out of the control gate. In this manner, the damage done on the tunnel insulating film can be reduced and the considerable decrease in reliability of the flash memory is avoidable.
The known method of reducing the charge buildup damage in a metallization process, however, has the following two drawbacks.
Firstly, a negative voltage with a large absolute value cannot be applied to the control gate. As a flash memory cell has been downsized recently, it becomes more and more necessary to reduce the positive high voltage (e.g., about 12 V) applied to the source electrode during an erase operation. Various techniques of reducing the source voltage have been proposed. One of those methods is a gate negative voltage erase method as represented in the following Table 1:
During a write operation, 12 V, 5 V, 0 V (i.e., ground potential) and 0 V are applied to the control gate, drain, source and p-well 111 of a selected flash memory cell, respectively. In this combination of applied voltages, channel hot electrons are created near the drain and are injected into the floating gate. After the write operation is over, the flash memory cell has a threshold voltage of about 6 V. As for non-selected flash memory cells on the other hand, 0 V is applied to the control gate thereof and the drain thereof is opened, thereby preventing those cells from being written erroneously.
During an erase operation, xe2x88x928 V, 5 V and 0 V are applied to the control gate, source and p-well 111 of the selected flash memory cell and the drain thereof is opened. In this combination of applied voltages, a Fowler-Nordheim (FN) tunneling current flows from the floating gate into the source and the electrons are removed from the floating gate. After the erase operation is over, the flash memory cell has a threshold voltage of about 2 V. As for the non-selected flash memory cells on the other hand, 0 V is applied to the control gate and source thereof, thereby preventing those cells from being erased erroneously.
During a read operation, 5 V, 1 V, 0 V and 0 V are applied to the control gate, drain, source and p-well 111 of the selected flash memory cell, respectively. In this combination of applied voltages, where the memory cell selected has been erased, a current flows from the drain toward the source thereof. On the other hand, if the selected cell has been written, no current flows through the cell. Accordingly, by sensing a difference in the amount of current flowing from the drain to the source thereof, it is possible to determine whether the memory cell has been erased or written. As for non-selected flash memory cells on the other hand, the ground potential is applied to the control gate thereof and the drain thereof is opened, thereby preventing those cells from being read erroneously.
However, the known charge buildup damage reducer for metallization process is not applicable to a flash memory cell to which this gate negative voltage erase method is supposed to be applied. This is because the negative voltage of xe2x88x928 V applied to the control gate thereof during the erase operation belongs to the voltage range in which the backward diode is forward biased, and cannot be applied to the control gate even when the damage reducer is used.
Secondly, the decrease in reliability of a flash memory cell is not completely avoidable because a positive high voltage of about 15 V might be applied to the control gate during a metallization process. Specifically, the known charge buildup damage reducer uses a backward diode, so a voltage between V11 (about xe2x88x920.6 V) and V12 (about 15 V) may be applied to the control gate. This voltage of about 15 V does not degrade the reliability of the flash memory so seriously but is so high as to allow a large FN tunneling current to flow through the tunnel insulating film thereof. Accordingly, the flash memory might have its reliability affected non-negligibly.
For these reasons, the known charge buildup damage reducing method for metallization process is not applicable to a flash memory utilizing the gate negative voltage erase method. Also, even if that damage reducing method is applied to a cell utilizing the erase method, the two problems mentioned above should occur and the charge buildup damage could not be reduced sufficiently during the metallization process.
It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device to which the gate negative voltage erase method and the charge buildup damage reducing method for metallization process are both applicable effectively.
To achieve this object, while a memory cell is operating, the damage reducer, which is a type of electrostatic discharge (ESD) shielding so to speak, is disabled according to the present invention.
Specifically, an inventive nonvolatile semiconductor memory device includes memory cell, charge buildup damage reducer and damage reducer control means. The memory cell includes floating and control gates formed over a semiconductor substrate. The damage reducer is connected to the control gate. And the control means is connected to the damage reducer. The damage reducer controls a potential level at the control gate so that the potential level falls within a predetermined voltage range even if charge buildup occurs in the control gate during a metallization process. And the control means allows no current to flow through the damage reducer while the memory cell is being written, read or erased.
The inventive memory device can adopt the gate negative voltage erase method and yet can reduce the charge buildup damage during a metallization process. Accordingly, the memory cell can operate at a reduced voltage.
In one embodiment of the present invention, the damage reducer is preferably a diode that includes first and second electrodes. The first electrode of the diode is preferably connected to the control gate. And the control means is preferably connected to the second electrode of the diode and preferably changes a voltage applied to the second electrode of the diode depending on whether the memory cell is being written, read or erased.
In this particular embodiment, the diode preferably includes: a well of a first conductivity type, which is formed in the substrate and used as the second electrode; and a doped region of a second conductivity type, which is defined in the well and used as the first electrode.
More particularly, the first and second conductivity types may be n- and p-types, respectively. And the control means may set the potential level at the n-well to a value equal to or greater than each voltage applied to the control gate while the memory cell is being written, read or erased.
In such an embodiment, the diode is connected in the forward direction. Accordingly, while the diode is reverse biased with respect to the control gate, no current flows through the diode and the device is compatible with the gate negative voltage erase method. Also, during a write operation, for example, a positive bias is applied to the control gate. However, since the control means sets the potential level at the n-well to a value equal to or greater than the positive bias, no forward current flows through the diode. Accordingly, the write operation can be performed just as intended.
Alternatively, the first and second conductivity types may also be p- and n-types, respectively. And the control means may set the potential level at the p-well to a value equal to or smaller than each voltage applied to the control gate while the memory cell is being written, read or erased.
In such an embodiment, the diode is connected in the backward direction. Accordingly, while the diode is forward biased with respect to the control gate, no current flows through the diode and the device can cope with the write and read operations as it is. Also, during an erase operation, a negative bias is applied to the control gate. However, since the control means sets the potential level at the p-well to a value equal to or smaller than the negative bias, no forward current flows through the diode. Accordingly, the erase operation can be performed just as intended.
In still another embodiment, the potential level at the control gate during the metallization process is preferably controlled to fall within a voltage range in which neither forward nor back current flows through the diode.
In yet another embodiment, the device preferably further includes a multi-level interconnect structure formed over the substrate to have two or more interconnect layers. The control gate and the diode are preferably connected together via one of the interconnect layers that is closer to the substrate than any other interconnect layer in the interconnect structure.
Then, the charge buildup damage can be reduced in every interconnect layer of the multi-level interconnect structure, as well as in the first-level interconnect layer.
In yet another embodiment, the damage reducer may include first and second diodes formed in the substrate. Each diode includes two electrodes with mutually opposite polarities. One of the two electrodes of the first diode and one of the two electrodes of the second diode may be both connected to the control gate. Then, the control means preferably changes a voltage applied to the other electrode of the first diode and the other electrode of the second diode depending on whether the memory cell is being written, read or erased.
In this particular embodiment, the first diode preferably includes a first well of a first conductivity type and a first doped region of a second conductivity type. The first well is formed in the substrate and used as the second electrode of the first diode. The first doped region is defined in the first well and used as the first electrode of the first diode. The second diode preferably includes a second well of the second conductivity type and a second doped region of the first conductivity type. The second well is formed in the substrate and used as the second electrode of the second diode. And the second doped region is defined in the second well and used as the first electrode of the second diode.
More particularly, the first and second conductivity types are preferably n- and p-types, respectively. The control means preferably sets the potential level at the n-well of the first diode to a value equal to or greater than each voltage applied to the control gate while the memory cell is being written, read or erased. Also, the control means preferably sets the potential level at the p-well of the second diode to a value equal to or smaller than each said voltage applied to the control gate while the memory cell is being written, read or erased.
In such an embodiment, the first and second diodes are connected in forward and backward directions, respectively. Accordingly, if positive charges build up during a metallization process, then the first diode is forward biased and the charges accumulated easily flow out therefrom. On the other hand, if negative charges build up during the metallization process, then the second diode is forward biased and the charges accumulated also flow out easily therefrom. Thus, the damage usually done on the tunnel insulating film can be eliminated almost completely. In addition, during a write or read operation in which the control gate is forward biased, the control means sets the potential level at the n-well of the first diode to a value equal to or greater than the positive bias. Accordingly, no forward current flows through the first diode. On the other hand, during an erase operation in which the control gate is reverse biased, the control means sets the potential level at the p-well of the second diode to a value equal to or smaller than the negative bias. Accordingly, no forward current flows through the second diode. In this manner, the memory cell can be written, read or erased just as intended.
In still another embodiment, the potential level at the control gate during the metallization process is preferably controlled to fall within a voltage range in which no forward current flows through the first or second diode.
In yet another embodiment, the inventive device preferably further includes a multi-level interconnect structure formed over the substrate to include two or more interconnect layers. The control gate is preferably connected to the first and second diodes via one of the interconnect layers that is closer to the substrate than any other interconnect layer in the interconnect structure.